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Job Information
- Organisation/Company: INESC TEC
- Research Field: Computer science » Informatics; Computer science » Digital systems; Engineering » Electronic engineering
Offer Description
Portuguese version: https://www.inesctec.pt/editais/pt/AE2026-0321.pdf
CALL FOR GRANT APPLICATIONS (AE2026-0321)
INESC TEC is now accepting grant applications to award 1 Research Initiation Grant (BII) within the scope of the on the scope ODE4ECDIG with reference 101252715 funded by the European Commission under the Horizon Europe program for the period 2021-2027.
1. GRANT DESCRIPTION
Type of grant: Research Initiation Grant (BII)
General scientific area: COMPUTER SCIENCE, ENGINEERING
Scientific subarea: Digital systems, Informatics, Electronic engineering
Grant duration: 6 months, starting on 2026-12-01, with the possibility of being renewed for a maximum term of one year.
Scientific advisor: João Bispo
Workplace: INESC TEC, Porto, Portugal
Maintenance stipend: 701.12, according to the table of monthly maintenance stipend for FCT grants (https://www.fct.pt/wp-content/uploads/2024/02/Tabela-de-Valores-SMM_atualizacao-2024.pdf), paid via bank transfer. Grant holders may be awarded potential supplements, according to a quarterly evaluation process (Articles 19, 21 and 22 of the Regulations for Grants of INESC TEC and Annex II), up to a maximum limit of 50 of the monthly maintenance stipend.
INESC TEC supports costs with registration, enrolment or tuition fees, during the grant duration, under the terms established in the internal document: "Payment of Tuition fees to grant holders" (https://www.inesctec.pt/pagamento-propinas-bolseirosEN)
The grant holder will benefit from health insurance, supported by INESC TEC.
2. OBJECTIVES:
High-level synthesis from C/C++ descriptions allows for an increased level of abstraction in digital hardware development, reducing the effort required to explore different architectures and implementation technologies. However, the integration of open-source HLS tools with end-to-end implementation flows for FPGAs and ASICs remains relatively unexplored. This work explores a workflow based on Bambu for high-level synthesis and LibreLane for ASIC implementation, evaluating its application to different architectures and numerical representations.
Specific Objectives:
- Explore and evaluate open-source high-level synthesis (HLS) methodologies for generating synthesizable hardware from C/C++ descriptions, with a focus on FPGA and ASIC implementation workflows.
- Evaluate the impact of alternative arithmetic and data representations, such as LNS and BF16, on the resulting hardware implementations.
- Co-author a scientific article to disseminate the results obtained.
3. BRIEF PRESENTATION OF THE WORK PROGRAMME AND TRAINING:
- Configure and characterize an open-source HLS flow based on Bambu [1], using representative hardware designs described in C/C++ and evaluating the generated RTL.
- Evaluate the integration of the generated designs with open-source synthesis flows for FPGAs and ASICs [2], comparing the quality of the implementations and identifying limitations of the flows.
- Apply the developed workflow to representative case studies, potentially including an in-house RISC-V processor developed in C++ and HLS-oriented.
- Evaluate selected arithmetic and data representations (e.g., LNS and BF16) using synthesis metrics such as area/resource utilization, temporal performance, and, when available, power consumption.
- Collaborate on writing a scientific paper to disseminate the results.
4. REQUIRED PROFILE:
Admission requirements:
Enrollment in a degree or master's degree program in electrical engineering, computer science, or a related field
The awarding of the fellowship is dependent on the applicants' enrolment in study cycle or non-award courses of Higher Education Institutions.
Preference factors:
- Experience with development or synthesis for FPGAs and/or ASICs;
- Familiarity with C/C++ for the description and implementation of digital systems;
- Fluent in Portuguese and English (written and spoken)
Minimum requirements:
- Experience in C/C++ programming
- Basic knowledge of digital systems and computer architectures
- Fluent in English (written and spoken)
5. EVALUATION OF APPLICATIONS AND SELECTION PROCESS:
Selection criteria and corresponding valuation: the first phase comprises the Academic Evaluation (AC), based on the criteria referred to in Article 12 of the Regulations for Grants of INESC TEC, while the second phase comprehends the Individual Interview (EI).
All factors are evaluated on a scale of 0 to 100, taking into account the applicants' merit, suitability and conformity with the preference factors.
The weight of the AC factors are as follows: Academic Qualifications (FA, 40), Scientific Publications (PC, 10), Experience (EX, 40) and Motivation Letter (CM, 10).
Candidates who score less than 50 points in the AC average will be considered excluded on absolute merit. The top five candidates approved on absolute merit will be qualified for the individual interview. The Final Grade (CF) is obtained by the weighted average of AC (70) and EI (30).
DISABILITY INCENTIVE
Candidates who present a degree of disability equal to or greater than 90% will benefit from an incentive (20) in the score of the CV Assessment.
Candidates who present a degree of disability equal to or greater than 60% and less than 90% will also benefit from an incentive (10) in the score of the CV Assessment.
Said score may, in these cases, exceed 100 points.
Candidates must demonstrate the degree of disability during the application, namely through the submission of the Multi-Purpose Medical Certificate of Disability, issued in accordance with Decree-Law no. 202/96, of October 23 - currently in effect.
The Selection Jury is composed of the following members:
President of the Jury: João Bispo
Full member: Filipe Figueiredo Correia
Full member: Nuno Miguel Paulino
Substitute member: Luis Miguel Pinho
Release of results and prior hearing: the results of the selection process, as well as the terms and procedures for prior hearing, will be released to the applicants by email, under the terms referred to in Article 13 of the Regulations for Studentships and Fellowships of INESC TEC.
6. FORMALISATION OF APPLICATIONS:
Application Documents:
- Motivation letter;
- Curriculum Vitae (must include the list of previous fellowships, their type, beginning and end dates, funding entities and host institutions);
- Certificate or diploma degree;
- Proof of enrollment in a degree awarding study cycle or in a non degree awarding Higher Education program. The proof of enrollment may be presented just during the grant hiring stage.
- Signed declaration stating not having benefited from any other research fellowship (Article 5, no. 5)
- Documental evidence to support the country of residence, residence permit or other legally equivalent document, in cases where the applicant is a foreigner or non-resident in Portugal - valid until the beginning of the grant.
- Other supporting documents relevant to the final assessment.
Failure to deliver the required documents within the 90-day period after the date of the notice of the conditional awarding of the grant implies its cancellation.
Application period: From 2026-10-22 to 2026-11-04
Submission of applications: the application will be formalised by submitting the form available in the Work With Us section of INESC TEC website.
7. BINDING LEGISLATION AND REGULATION
The hiring process shall comply with the current legislation regarding the Research Grant Holder Statute, approved by Law no. 40/2004 of August 18, in its current wording, as well as by the Regulations for Grants of INESC TEC and for FCT Grants Regulation in force.
For more information, please check the Regulations for Grants of INESC TEC and relevant annexes at www.inesctec.pt/bolsas
Where to apply
Website: https://www.inesctec.pt/en/opportunity/AE2026-0321
Requirements
Specific Requirements
Academic qualifications: Enrollment in a degree or master's degree program in electrical engineering, computer science, or a related field.
Minimum profile: Experience in C/C++ programming, basic knowledge of digital systems and computer architectures, fluent in English (written and spoken).
Preference factors: Experience with development or synthesis for FPGAs and/or ASICs; familiarity with C/C++ for the description and implementation of digital systems; fluent in Portuguese and English (written and spoken).
- Research Field: Computer science » Informatics — Years of Research Experience: None
- Research Field: Computer science » Digital systems — Years of Research Experience: None
- Research Field: Engineering » Electronic engineering — Years of Research Experience: None
Additional Information
Benefits
Maintenance stipend: 701.12 euros, according to the table of monthly maintenance stipend for FCT grants (https://www.fct.pt/wp-content/uploads/2024/02/Tabela-de-Valores-SMM_atualizacao-2024.pdf), paid via bank transfer. Grant holders may be awarded potential supplements, according to a quarterly evaluation process (Articles 19, 21 and 22 of the Regulations for Grants of INESC TEC and Annex II), up to a maximum limit of 50% of the monthly maintenance stipend.
Costs attributable to INESC TEC may include registration, enrolment or tuition fee stipend, either directly or through reimbursement, during the grant duration.
The grant holder will benefit from health insurance, supported by INESC TEC.
Selection process
Selection criteria and corresponding valuation: the first phase comprises the Academic Evaluation (AC), based on the criteria referred to in Article 12 of the Regulations for Grants of INESC TEC, while the second phase comprehends the Individual Interview (EI).
All factors are evaluated on a scale of 0 to 100, taking into account the applicants' merit, suitability and conformity with the preference factors.
The weight of the AC factors are as follows: Academic Qualifications (FA, 40), Scientific Publications (PC, 10), Experience (EX, 40) and Motivation Letter (CM, 10).
Candidates who score less than 50 points in the AC average will be considered excluded on absolute merit. The top five candidates approved on absolute merit will be qualified for the individual interview. The Final Grade (CF) is obtained by the weighted average of AC (70) and EI (30).
DISABILITY INCENTIVE
Candidates who present a degree of disability equal to or greater than 90% will benefit from an incentive (20) in the score of the CV Assessment. Candidates who present a degree of disability equal to or greater than 60% and less than 90% will also benefit from an incentive (10) in the score of the CV Assessment. Said score may, in these cases, exceed 100 points.
Candidates must demonstrate the degree of disability during the application, namely through the submission of the Multi-Purpose Medical Certificate of Disability, issued in accordance with Decree-Law no. 202/96, of October 23 - currently in effect.
The Selection Jury is composed of the following members: President of the Jury: João Bispo; Full member: Filipe Figueiredo Correia; Full member: Nuno Miguel Paulino; Substitute member: Luis Miguel Pinho
Release of results and prior hearing: the results of the selection process, as well as the terms and procedures for prior hearing, will be released to the applicants by email, under the terms referred to in Article 13 of the Regulations for Studentships and Fellowships of INESC TEC.
Website for additional job details: https://www.inesctec.pt/en/opportunity/AE2026-0321
Work Location(s)
- Number of offers available: 1
- Company/Institute: INESC TEC
- Country: Portugal
- City: Porto
- Postal Code: 4200-465
- Street: Campus da Faculdade de Engenharia da Universidade do Porto, Rua Dr. Roberto Frias
Contact
- City: Porto
- Website: http://www.inesctec.pt
- Street: Campus da FEUP - Rua Dr. Roberto Frias
- Postal Code: 4200-465 Porto