Secure and Resilient Computing: New computer architectures for more secure and low-energy devices and systems.

The candidate will pursue one of the three complementary strands, each sharing a methodological core of Secure and Resilient Computing Architectures:

Strand 1: Fault-Tolerant Hardware Architectures for Post-Quantum Cryptographic Systems

(Lead: Dr. Yasir Ali Shah)

As post-quantum cryptographic (PQC) algorithms become essential for securing next-generation communications and critical infrastructure, ensuring their reliability in hardware implementations is a major challenge. This PhD project will investigate fault-tolerant cryptographic kernels that provide runtime error detection and correction with minimal area, power, and performance overheads.

The research will develop lightweight redundancy and resilience techniques for key PQC operations, including modular arithmetic, Number Theoretic Transforms (NTTs), and polynomial computations. The goal is to create secure and dependable cryptographic hardware capable of resisting natural faults and fault-injection attacks, enabling trustworthy deployment in resource-constrained, safety-critical, and high-performance computing environments.

or Strand 2:

Design and Evaluation of Physical Unclonable Functions (PUFs) in Neural Hardware for Secure Edge AI

(Lead: Dr. Aditya Japa)

The advancement of artificial intelligence (AI) and machine learning has driven neural network accelerators (NNAs) for workloads, including applications such as medical diagnosis and autonomous driving. However, readout, fault injection, bit-flip, and side-channel attacks can expose training data, model parameters, and accelerator architectures.

Physical Unclonable Functions (PUFs) provide security by exploiting process variations to generate responses, enabling authentication, secure key generation, and protection of assets. Conventional PUFs face challenges in NNAs due to power, reliability, scalability, and robustness requirements.

This PhD project exploits neural hardware variability and randomness to develop PUFs, assessing security, uniqueness, randomness, area, power, robustness, and latency.

or Strand 3:

Low-Energy AI Hardware for High-Performance Computing (HPC)

(Lead: Prof Jim Harkin)

The rapid growth of AI is increasing data centre energy consumption, driven largely by power-intensive GPU architectures. This PhD will investigate alternative low-energy computing approaches, focusing on neuromorphic and event-based architectures inspired by the efficient information processing of the human brain.

The research will explore novel hardware architectures and accelerators for event-based AI applications, targeting improved energy efficiency without compromising performance. FPGA-based platforms will be used to prototype and evaluate these approaches, integrating with High-Performance Computing (HPC) infrastructure to enable benchmarking against conventional GPU-based systems. The project aims to advance sustainable, energy-efficient AI hardware for future HPC and data centre environments.

Funding Notes

OPEN TO HOME AND REPUBLIC OF IRELAND STUDENTS ONLY

References

1. Ziying Ni, Ayesha Khalid, Yijun Cui, Weiqiang Liu, and Máire O’Neill. 2026. Real-time, Lightweight, High Coverage Error Detection and Correction for CRYSTALSwithSmall-ModulusPaths. 63rd ACM/IEEEDesignAutomation Conference (DAC ’26), July 26–29, 2026, Long Beach, CA, USA. ACM, New York, NY, USA, 7 pages.
2. Khan, Safiullah, Ayesha Khalid, Ciara Rafferty, Yasir Ali Shah, Maire O’Neill, Wai-Kong Lee, and Seong Oun Hwang. "Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators." In 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1-6. IEEE, 2023.
3. Ensuring trust in AI to unlock £6.5 billion over next decade [Online]. Available: https://www.gov.uk/government/news/ensuring-trust-in-ai-to-unlock-65-billion-over-next-decade
4. K. Lee et al., “Secure Machine Learning Hardware: Challenges and Progress [Feature],” in IEEE Circuits and Systems Magazine, vol. 25, no. 1, pp. 8-34, Firstquarter 2025. (doi: 10.1109/MCAS.2024.3509376)